1. Technical Field
The present invention relates to a clock generating device that generates a clock signal and a jitter reducing method in the clock generating device.
2. Related Art
In the past, there is known a clock generating device employing a DDS (Direct Digital Synthesizer) circuit that generates a periodic signal.
In the clock generating device employing the DDS circuit, in the DDS circuit, a phase accumulator that adds up phases by a value Δphase, which determines angular velocity of a generation frequency, at a time sequentially accumulates and adds up Δphase and, as a result of the accumulation and addition, sequentially outputs, as a digital value, a phase θ for generating angular velocity of a predetermined periodic signal.
The amplitude of a sine wave is acquired as a digital value by a sine-wave converting unit that converts the phase θ into the amplitude of the sine wave.
The amplitude of the sine wave output in this way is converted into an analog signal by a D/A (Digital to Analog) converter, processed through a LPF (Low Pass Filter) in order to remove sampling noise and quantization noise, and output as an output signal of the DDS circuit.
Then, a sine wave signal of a single spectrum is obtained at the output of the DDS circuit.
The sine wave signal is input to a comparator and compared with a reference value of amplitude (e.g., amplitude zero) to output a binarized signal.
Consequently, a clock signal at a fixed cycle can be obtained.
A technique concerning the clock generating device employing the DDS circuit is described in, for example, JP-A-10-41748.
However, in the clock generating device employing the DDS circuit including the technique described in JP-A-10-41748, when a frequency of a clock signal to be generated is reduced, a rate of change (an amount of change per unit time, i.e., changing speed, e.g., in the case of a voltage signal, dV/dt) of an input signal near crossing with the reference value falls. This makes it difficult to generate a clock signal with less jitter.
This is considered to be because, when the rate of change of the input signal near the crossing with the reference value falls in a comparator, the influence of noise on timing of actual crossing increases.